Capacitance to Voltage Meter Circuit Diagram

Build a simple Capacitance to Voltage Meter Circuit Diagram. In this volt meter circuit uses timer Ul operates as a free-running oscillator at 60 Hz, providing trigger pulses to timer U2 which operates in the monostable mode. Resistor Rl is fixed and capacitor Cx is the capacitor being measured.

Capacitance to Voltage Meter Circuit Diagram

While the output of U2 is 60 Hz, the duty cycle depends on the value of Cx. U3 is a combination low-pass filter and unity-gain follower whose dc voltage output is the time-averaged amplitude of the output pulses of U2, as shown in the timing diagram. The diagram shows when the value of Cx is small the duty cycle is relatively low. The output pulses are narrow and produce a lower average dc voltage level at the output of U3.

As the capacitance value of Cx increases, the duty cycle increases making the output pulses at U2 wider and the average dc level output at U3 increases. The graph illustrates capacitance values of 0.01 ?¥ to 0.1 ?¥ plotted against the output voltage of U3. Notice the excellent linearity and direct one-to-one scale calibration of the meter. If this does not occur the 100 k ohm resistor, Rl, can be replaced with a potentiometer which can be adjusted to the proper value for the meter being used.

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